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Re: [PATCH 0/6] MIPS Read Inhibit/eXecute Inhibit support (v2).

To: David Daney <ddaney@caviumnetworks.com>
Subject: Re: [PATCH 0/6] MIPS Read Inhibit/eXecute Inhibit support (v2).
From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 11 Feb 2010 00:56:49 +0100
Cc: linux-mips <linux-mips@linux-mips.org>
In-reply-to: <4B733C71.8030304@caviumnetworks.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <4B733C71.8030304@caviumnetworks.com>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.5.20 (2009-08-17)
On Wed, Feb 10, 2010 at 03:08:33PM -0800, David Daney wrote:

> This patch set adds execute and read inhibit support.  By default glibc
> based tool chains will create mappings for data areas of a program and
> shared libraries with PROT_EXEC cleared.  With this patch applied, a
> SIGSEGV is correctly sent if an attempt is made to execute from data
> areas.
> 
> The first three patch just make a few tweaks in preperation for the
> main body of the patch in 4/6.  The last two turn on the feature for
> some Octeon CPUs.
> 
> I will reply with the six patches.
> 
> David Daney (6):
>   MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels.
>   MIPS: Add accessor functions and bit definitions for c0_PageGrain
>   MIPS: Add TLBR and ROTR to uasm.
>   MIPS: Implement Read Inhibit/eXecute Inhibit
>   MIPS: Give Octeon+ CPUs their own cputype.
>   MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs

Hangs on IP27 after

[...]
Calibrating delay loop... 178.17 BogoMIPS (lpj=89088)
Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)

  Ralf

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