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[PATCH 6/6] MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs

To: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: [PATCH 6/6] MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs
From: David Daney <ddaney@caviumnetworks.com>
Date: Wed, 10 Feb 2010 15:12:49 -0800
Cc: David Daney <ddaney@caviumnetworks.com>
In-reply-to: <4B733C71.8030304@caviumnetworks.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <4B733C71.8030304@caviumnetworks.com>
Sender: linux-mips-bounce@linux-mips.org
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h 
b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 425e708..bbf0540 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -58,6 +58,9 @@
 #define cpu_has_vint           0
 #define cpu_has_veic           0
 #define cpu_hwrena_impl_bits   0xc0000000
+
+#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == 
CPU_CAVIUM_OCTEON_PLUS)
+
 #define ARCH_HAS_READ_CURRENT_TIMER 1
 #define ARCH_HAS_IRQ_PER_CPU   1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1
-- 
1.6.2.5


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