[PATCH 2/6] MIPS: Add accessor functions and bit definitions for c0_PageGrain

[David Daney <ddaney@caviumnetworks.com>]

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 arch/mips/include/asm/mipsregs.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index b30819c..9893758 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -251,6 +251,14 @@
 #define PL_256M                28
 
 /*
+ * PageGrain bits
+ */
+#define PG_RIE         (_ULCAST_(1) <<  31)
+#define PG_XIE         (_ULCAST_(1) <<  30)
+#define PG_ELPA                (_ULCAST_(1) <<  29)
+#define PG_ESP         (_ULCAST_(1) <<  28)
+
+/*
  * R4x00 interrupt enable / cause bits
  */
 #define IE_SW0          (_ULCAST_(1) <<  8)
@@ -840,6 +848,9 @@ do {                                                        
                \
 #define read_c0_pagemask()     __read_32bit_c0_register($5, 0)
 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
 
+#define read_c0_pagegrain()    __read_32bit_c0_register($5, 1)
+#define write_c0_pagegrain(val)        __write_32bit_c0_register($5, 1, val)
+
 #define read_c0_wired()                __read_32bit_c0_register($6, 0)
 #define write_c0_wired(val)    __write_32bit_c0_register($6, 0, val)
 
-- 
1.6.2.5