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Re: [PATCH v3] Virtual memory size detection for 64 bit MIPS CPUs

To: Guenter Roeck <guenter.roeck@ericsson.com>
Subject: Re: [PATCH v3] Virtual memory size detection for 64 bit MIPS CPUs
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 2 Feb 2010 12:42:59 +0100
Cc: David Daney <ddaney@caviumnetworks.com>, "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>, "Maciej W. Rozycki" <macro@linux-mips.org>
In-reply-to: <20100202001026.GA6883@ericsson.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <1265064686-31278-1-git-send-email-guenter.roeck@ericsson.com> <4B676755.10600@caviumnetworks.com> <20100202001026.GA6883@ericsson.com>
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On Mon, Feb 01, 2010 at 04:10:26PM -0800, Guenter Roeck wrote:

> > > + if (cpu_has_64bits) {
> > > +         write_c0_entryhi(0xfffffffffffff000ULL);
> > 
> > macro indicated that we need to avoid hazards here on R4000.

A MTC0 instruction on an R4000 writes EntryHi on pipeline stage 7 but
will read from the same register on stage 4 which leaves a window of
2 instructions, that is 2 NOP instructions needed.

> > Perhaps adding:
> > 
> >     back_to_back_c0_hazard();
> > 
> Compiler already added a nop, so I thought it wasn't necessary.
> Doesn't hurt either, so I'll put it in.

This probe is needed as per MIPSxx architecture spec and several CPUs will
missbehave without it.  The 74K which of course is 32-bit but it
illustrates the issue might even issue these instructions out of order.
back_to_back_c0_hazard will expand into a suitable sequence to handle
the pipeline hazard.  And we can't trust on the compiler doing the right
thing here; as explained above we might need multiple nops and some CPUs
will need other instructions to deal with the hazard, for example a number
of SSNOPs or an EHB instruction.

  Ralf

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