linux-mips
[Top] [All Lists]

[PATCH -queue 1/3] MIPS: add a common mips_sched_clock()

To: Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH -queue 1/3] MIPS: add a common mips_sched_clock()
From: Wu Zhangjin <wuzhangjin@gmail.com>
Date: Mon, 1 Feb 2010 19:13:10 +0800
Cc: David Daney <ddaney@caviumnetworks.com>, "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>, Wu Zhangjin <wuzhangjin@gmail.com>
Dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=t7okXqjZNkmvJrjNBkLmk7wO3rQO1Zp6jlZQvNd/cBQ=; b=cv5B5RQGxlMhNUOP0oa49ULuHAc4lKqVrkRkc2krTRK/UvDF6yiHwHOeIFVW1A4/Nj D+cy/SikJIML7QGX+yeSFy5zhftnyog4Qs2hLKI5HLLKXpP0nZPXB3njdS7jFgEoZETc OuDZIwHXp5kx1gdmJaAKJD0v6x1FL/qo2jm9s=
Domainkey-signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=kaTbFBWIvwub4beQVwZQF+D7+/1aWpEaILs4NBWJ2c5OmVYgqavhxL5pSZlIMzHj3r BLrtwS7npklGrGMM8mK4QzdxgmBxHi4dQC3rUm8edwIsSgb8z/sIPMDRCXdWsj1De5j9 0FsjGnn9Vrp3IYpZ/hUW5zDtkeWXRk8t9kG+A=
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
From: Wu Zhangjin <wuzhangjin@gmail.com>

Because the high resolution sched_clock() for r4k has the same overflow
problem and solution mentioned in "MIPS: Octeon: Use non-overflowing
arithmetic in sched_clock".

    "With typical mult and shift values, the calculation for Octeon's
    sched_clock overflows when using 64-bit arithmetic.  Use 128-bit
    calculations instead."

To reduce the duplication, This patch abstracts the solution into an
inline funciton mips_sched_clock() into arch/mips/include/asm/time.h
from arch/mips/cavium-octeon/csrc-octeon.c.

Two patches for Cavium and R4K will be sent out respectively to use this
common function.

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
---
 arch/mips/include/asm/time.h |   30 ++++++++++++++++++++++++++++++
 1 files changed, 30 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index c7f1bfe..f7bd5ce 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -96,4 +96,34 @@ static inline void clockevent_set_clock(struct 
clock_event_device *cd,
        clockevents_calc_mult_shift(cd, clock, 4);
 }
 
+static inline unsigned long long mips_sched_clock(struct clocksource *cs, u64 
cnt)
+{
+       /* 64-bit arithmatic can overflow, so use 128-bit.  */
+#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3))
+       u64 t1, t2, t3;
+       unsigned long long rv;
+       u64 mult = cs->mult;
+       u64 shift = cs->shift;
+
+       asm (
+               "dmultu\t%[cnt],%[mult]\n\t"
+               "nor\t%[t1],$0,%[shift]\n\t"
+               "mfhi\t%[t2]\n\t"
+               "mflo\t%[t3]\n\t"
+               "dsll\t%[t2],%[t2],1\n\t"
+               "dsrlv\t%[rv],%[t3],%[shift]\n\t"
+               "dsllv\t%[t1],%[t2],%[t1]\n\t"
+               "or\t%[rv],%[t1],%[rv]\n\t"
+               : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" 
(t3)
+               : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
+               : "hi", "lo");
+       return rv;
+#else  /* GCC > 4.3 do it the easy way.  */
+       unsigned int __attribute__((mode(TI))) t = cnt;
+
+       t = (t * cs->mult) >> cs->shift;
+       return (unsigned long long)t;
+#endif
+}
+
 #endif /* _ASM_TIME_H */
-- 
1.6.6


<Prev in Thread] Current Thread [Next in Thread>