[PATCH 2/2] MIPS: Decode c0_config4 for large TLBs.

[David Daney <ddaney@caviumnetworks.com>]

For processors that have more than 64 TLBs, we need to decode both
config1 and config4 to determine the total number TLBs.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 arch/mips/include/asm/mipsregs.h |    3 +++
 arch/mips/kernel/cpu-probe.c     |   14 ++++++++++++++
 2 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 5c192a0..298216e 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -564,6 +564,9 @@
 #define MIPS_CONF3_DSP         (_ULCAST_(1) << 10)
 #define MIPS_CONF3_ULRI                (_ULCAST_(1) << 13)
 
+#define MIPS_CONF4_MMUSIZEEXT  (_ULCAST_(255) << 0)
+#define MIPS_CONF4_MMUEXTDEF   (_ULCAST_(3) << 14)
+
 #define MIPS_CONF7_WII         (_ULCAST_(1) << 31)
 
 #define MIPS_CONF7_RPS         (_ULCAST_(1) << 2)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 80e202e..517c565 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -691,6 +691,18 @@ static inline unsigned int decode_config3(struct 
cpuinfo_mips *c)
        return config3 & MIPS_CONF_M;
 }
 
+static inline unsigned int decode_config4(struct cpuinfo_mips *c)
+{
+       unsigned int config4;
+
+       config4 = read_c0_config4();
+
+       if ((config4 & MIPS_CONF4_MMUEXTDEF) == 0x4000 && cpu_has_tlb)
+               c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
+
+       return config4 & MIPS_CONF_M;
+}
+
 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 {
        int ok;
@@ -709,6 +721,8 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
                ok = decode_config2(c);
        if (ok)
                ok = decode_config3(c);
+       if (ok)
+               ok = decode_config4(c);
 
        mips_probe_watch_registers(c);
 }
-- 
1.6.0.6