[PATCH 0/2] Rearrange MIPS barriers and optimize for Octeon.

[David Daney <ddaney@caviumnetworks.com>]

Locking/atomic performance on Octeon can be improved by using
optimized barrier instructions.  The first patch in this set
rearranges and simplifies (at least in my mind) the existing barriers.
Then the second patch adds Octeon specific barriers.

I will reply with the two patches.

David Daney (2):
  MIPS: New macro smp_mb__before_llsc.
  MIPS: Octeon: Use optimized memory barrier primitives.

 arch/mips/Kconfig                |    1 -
 arch/mips/include/asm/atomic.h   |   16 ++++++------
 arch/mips/include/asm/barrier.h  |   52 
+++++++++++++++++++++++++++-----------
 arch/mips/include/asm/bitops.h   |    8 +++---
 arch/mips/include/asm/cmpxchg.h  |   10 +++---
 arch/mips/include/asm/spinlock.h |    4 +-
 arch/mips/include/asm/system.h   |    4 +++
 7 files changed, 60 insertions(+), 35 deletions(-)