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Re: PIR OFFSET for AR7

To: myuboot@fastmail.fm
Subject: Re: PIR OFFSET for AR7
From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Date: Fri, 4 Dec 2009 17:03:33 +0100
Cc: linux-kernel@vger.kernel.org, linux-mips <linux-mips@linux-mips.org>
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Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20091028103551.0b4052d8@pixies.home.jungo.com> <1259891550.19943.1348372917@webmail.messagingengine.com>
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On Thu, Dec 03, 2009 at 07:52:30PM -0600, myuboot@fastmail.fm wrote:
> Hi, What is the use of PIR register for AR7 board in file
> arch/mips/ar7/irq.c?

it gives back the channel and line of the pending interrupt with the
highest priority.

> If I understand it right, PIR is used to define the
> polarity of the interrupts. It seems to me that it needs to initialized?

no, it's a read only register. Why do you think it has something to do
with interrupt polarity ?

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea.                                                [ RFC1925, 2.3 ]

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