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Re: Syncing CPU caches from userland on MIPS

To: Florian Lohoff <flo@rfc822.org>
Subject: Re: Syncing CPU caches from userland on MIPS
From: Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
Date: Wed, 25 Nov 2009 15:39:01 +0100
Cc: Aurelien Jarno <aurelien@aurel32.net>, linux-mips@linux-mips.org
In-reply-to: <20091125140105.GB13938@paradigm.rfc822.org> (Florian Lohoff's message of "Wed\, 25 Nov 2009 15\:01\:05 +0100")
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References: <20091124182841.GE17477@hall.aurel32.net> <20091125140105.GB13938@paradigm.rfc822.org>
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Florian Lohoff <flo@rfc822.org> writes:
Hi,

> On Tue, Nov 24, 2009 at 07:28:41PM +0100, Aurelien Jarno wrote:
>> Hi all,
>> 
>> This question is not really kernel related, but still MIPS related, I
>> hope you don't mind.
>> 
>> Arnaud Patard and myself are trying to get qemu working on MIPS [1],
>> which includes translating TCG code (internal representation) into MIPS
>> instructions, that are then executed. Most of the code works, but we 
>> have some strange behaviors that seems related to CPU caches.
>> 
>> The code is written to a buffer, which is then executed. Before the
>> execution, the caches are synced using the cacheflush syscall:
>> 
>> | #include <sys/cachectl.h>
>> |  
>> | 
>> | static inline void flush_icache_range(unsigned long start, unsigned long 
>> stop)
>> | {
>> |     cacheflush ((void *)start, stop-start, ICACHE);
>> | }
>
> Would this only evict stuff from the ICACHE? When trying to execute
> a just written buffer and with a writeback DCACHE you would need to 
> explicitly writeback the DCACHE to memory and invalidate the ICACHE.

we already though about using BCACHE instead of ICACHE only but it
didn't make any difference. the bug is still there.

Arnaud

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