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Re: Syncing CPU caches from userland on MIPS

To: Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: Syncing CPU caches from userland on MIPS
From: Florian Lohoff <flo@rfc822.org>
Date: Wed, 25 Nov 2009 15:01:05 +0100
Cc: linux-mips@linux-mips.org, Arnaud Patard <arnaud.patard@rtp-net.org>
In-reply-to: <20091124182841.GE17477@hall.aurel32.net>
Organization: rfc822 - pure communication
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20091124182841.GE17477@hall.aurel32.net>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.5.18 (2008-05-17)
On Tue, Nov 24, 2009 at 07:28:41PM +0100, Aurelien Jarno wrote:
> Hi all,
> 
> This question is not really kernel related, but still MIPS related, I
> hope you don't mind.
> 
> Arnaud Patard and myself are trying to get qemu working on MIPS [1],
> which includes translating TCG code (internal representation) into MIPS
> instructions, that are then executed. Most of the code works, but we 
> have some strange behaviors that seems related to CPU caches.
> 
> The code is written to a buffer, which is then executed. Before the
> execution, the caches are synced using the cacheflush syscall:
> 
> | #include <sys/cachectl.h>
> |  
> | 
> | static inline void flush_icache_range(unsigned long start, unsigned long 
> stop)
> | {
> |     cacheflush ((void *)start, stop-start, ICACHE);
> | }

Would this only evict stuff from the ICACHE? When trying to execute
a just written buffer and with a writeback DCACHE you would need to 
explicitly writeback the DCACHE to memory and invalidate the ICACHE.

> It seems this is not enough, as sometimes, some executed code does not
> correspond to the assembly dump of this memory region. This seems to be 
> especially the case of memory regions that are written twice, due to
> relocations:
> 1) a branch instruction is written with an offset of 0
> 2) the offset is patched
> 3) cacheflush is called
> 
> Sometimes the executed code correspond to the code written in 1), which
> means the branch is skipped.

Which proves my theory - as long as you have cache pressure you will happily
writeback the contents to memory before trying to execute (you invalidate
the ICACHE above) - In case you DCACHE does not suffer from pressure
the contents will not been written back and you'll execute stale code.

Flo
-- 
Florian Lohoff                                         flo@rfc822.org
"Es ist ein grobes Missverständnis und eine Fehlwahrnehmung, dem Staat
im Internet Zensur- und Überwachungsabsichten zu unterstellen."
- - Bundesminister Dr. Wolfgang Schäuble -- 10. Juli in Berlin 

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