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Re: Syncing CPU caches from userland on MIPS

To: David Daney <ddaney@caviumnetworks.com>
Subject: Re: Syncing CPU caches from userland on MIPS
From: Aurelien Jarno <aurelien@aurel32.net>
Date: Tue, 24 Nov 2009 22:35:22 +0100
Cc: linux-mips@linux-mips.org, Arnaud Patard <arnaud.patard@rtp-net.org>
In-reply-to: <4B0C4A77.9020103@caviumnetworks.com>
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References: <20091124182841.GE17477@hall.aurel32.net> <4B0C4A77.9020103@caviumnetworks.com>
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On Tue, Nov 24, 2009 at 01:04:55PM -0800, David Daney wrote:
> Aurelien Jarno wrote:
>> Hi all,
>>
>> This question is not really kernel related, but still MIPS related, I
>> hope you don't mind.
>>
>> Arnaud Patard and myself are trying to get qemu working on MIPS [1],
>> which includes translating TCG code (internal representation) into MIPS
>> instructions, that are then executed. Most of the code works, but we  
>> have some strange behaviors that seems related to CPU caches.
>>
>> The code is written to a buffer, which is then executed. Before the
>> execution, the caches are synced using the cacheflush syscall:
>>
>> | #include <sys/cachectl.h>
>> |  | | static inline void flush_icache_range(unsigned long start, 
>> unsigned long stop)
>> | {
>> |     cacheflush ((void *)start, stop-start, ICACHE);
>> | }
>>
>> It seems this is not enough, as sometimes, some executed code does not
>> correspond to the assembly dump of this memory region. This seems to be 
>> especially the case of memory regions that are written twice, due to
>> relocations:
>> 1) a branch instruction is written with an offset of 0
>> 2) the offset is patched
>
> Try inserting an 'asm volatile ("sync" ::: "memory");' here.  If that  
> fixes things, then we can assume that your cacheflush system call is  
> buggy, and would need to add a sync.
>

That doesn't help, it still crashes at the same location.

Aurelien

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

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