linux-mips
[Top] [All Lists]

Syncing CPU caches from userland on MIPS

To: linux-mips@linux-mips.org
Subject: Syncing CPU caches from userland on MIPS
From: Aurelien Jarno <aurelien@aurel32.net>
Date: Tue, 24 Nov 2009 19:28:41 +0100
Cc: Arnaud Patard <arnaud.patard@rtp-net.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.5.18 (2008-05-17)
Hi all,

This question is not really kernel related, but still MIPS related, I
hope you don't mind.

Arnaud Patard and myself are trying to get qemu working on MIPS [1],
which includes translating TCG code (internal representation) into MIPS
instructions, that are then executed. Most of the code works, but we 
have some strange behaviors that seems related to CPU caches.

The code is written to a buffer, which is then executed. Before the
execution, the caches are synced using the cacheflush syscall:

| #include <sys/cachectl.h>
|  
| 
| static inline void flush_icache_range(unsigned long start, unsigned long stop)
| {
|     cacheflush ((void *)start, stop-start, ICACHE);
| }

It seems this is not enough, as sometimes, some executed code does not
correspond to the assembly dump of this memory region. This seems to be 
especially the case of memory regions that are written twice, due to
relocations:
1) a branch instruction is written with an offset of 0
2) the offset is patched
3) cacheflush is called

Sometimes the executed code correspond to the code written in 1), which
means the branch is skipped.

Does someone knows and/or has example code to correctly sync the CPU 
caches from userland on MIPS?

Thanks in advance,
Aurelien

[1] http://git.aurel32.net/?p=qemu.git;a=shortlog;h=refs/heads/tcg-mips

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

<Prev in Thread] Current Thread [Next in Thread>