linux-mips
[Top] [All Lists]

Re: why it not write those 6bits to entrylo0/1 register?

To: figo zhang <figo1802@gmail.com>
Subject: Re: why it not write those 6bits to entrylo0/1 register?
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 18 Nov 2009 15:08:09 +0100
Cc: linux-mips@linux-mips.org
In-reply-to: <c6ed1ac50911170137u7463ad53k1568e722696ca570@mail.gmail.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <c6ed1ac50911170012u7a52fbb9h1ae62cabf766122f@mail.gmail.com> <20091117084047.GA2923@linux-mips.org> <c6ed1ac50911170059w600de299kfe4d79916547d809@mail.gmail.com> <20091117092601.GB2923@linux-mips.org> <c6ed1ac50911170137u7463ad53k1568e722696ca570@mail.gmail.com>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.5.19 (2009-01-05)
On Tue, Nov 17, 2009 at 05:37:25PM +0800, figo zhang wrote:

> > > so, if i set a page attrubite is PAGE_READONLY, this attribute will set
> > to
> > > pte , right? so ,
> > > why it should shift 6 bits?
> >
> 
> Thanks a lot. I am puzzle that  if i set a page attrubite is PAGE_READONLY,
> tlb_write_indexed()
> will write the 6 bits to entrylo0 register? i am using 24KEC soc.

Yes, tlb_write_indexed() does that.  Equally tlb_write_random() writes a
TLB entry into the TLB.  Basically we use tlb_write_indexed() to overwrite
and update an existing TLB entry.  But if there is no TLB entry yet then
we just use tlb_write_random() an allow the CPU to pick an arbitrary entry.

  Ralf

<Prev in Thread] Current Thread [Next in Thread>