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Re: why it not write those 6bits to entrylo0/1 register?

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: why it not write those 6bits to entrylo0/1 register?
From: figo zhang <figo1802@gmail.com>
Date: Tue, 17 Nov 2009 16:59:59 +0800
Cc: linux-mips@linux-mips.org
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2009/11/17 Ralf Baechle <ralf@linux-mips.org>
On Tue, Nov 17, 2009 at 04:12:03PM +0800, figo zhang wrote:

> hi, all,
> i have a qusetion , in arch/mips/mm/tlb-r4k.c, __update_tlb() function:
>  321<http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=arch/mips/mm/tlb-r4k.c;h=d73428b18b0a41da13e81c64021e62505200ff2d;hb=317c68c04d53198f38314d29ba28b8fc632eccab#l321>#if
> defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
> 322<http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=arch/mips/mm/tlb-r4k.c;h=d73428b18b0a41da13e81c64021e62505200ff2d;hb=317c68c04d53198f38314d29ba28b8fc632eccab#l322>
>                write_c0_entrylo0(ptep->pte_high);
> 323<http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=arch/mips/mm/tlb-r4k.c;h=d73428b18b0a41da13e81c64021e62505200ff2d;hb=317c68c04d53198f38314d29ba28b8fc632eccab#l323>
>                ptep++;
> 324<http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=arch/mips/mm/tlb-r4k.c;h=d73428b18b0a41da13e81c64021e62505200ff2d;hb=317c68c04d53198f38314d29ba28b8fc632eccab#l324>
>                write_c0_entrylo1(ptep->pte_high);
> 325<http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=arch/mips/mm/tlb-r4k.c;h=d73428b18b0a41da13e81c64021e62505200ff2d;hb=317c68c04d53198f38314d29ba28b8fc632eccab#l325>#else
> 326<http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=arch/mips/mm/tlb-r4k.c;h=d73428b18b0a41da13e81c64021e62505200ff2d;hb=317c68c04d53198f38314d29ba28b8fc632eccab#l326>
>                write_c0_entrylo0(pte_val(*ptep++) >> 6);
> 327<http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=arch/mips/mm/tlb-r4k.c;h=d73428b18b0a41da13e81c64021e62505200ff2d;hb=317c68c04d53198f38314d29ba28b8fc632eccab#l327>
>                write_c0_entrylo1(pte_val(*ptep) >> 6);
> 328<http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=arch/mips/mm/tlb-r4k.c;h=d73428b18b0a41da13e81c64021e62505200ff2d;hb=317c68c04d53198f38314d29ba28b8fc632eccab#l328>#endif
>
> why this right shift 6 bits? this 6 bits contain some important bit, such
> as:
> C: [bit3~5]: cohereny attribute of page

No, the low 6 bits contain other information maintained by the kernel.
Shifting right by 6 bits is used to drop these software bits.  The
hardware bits are stored in bits 6 and up in a pte so the shift operation
is going to move them into the right place.
 
But i have see the kernel code: include/asm-mips/pgtable-bits.h:
#define _CACHE_UNCACHED             (2<<3)
#define _CACHE_CACHABLE_NONCOHERENT (3<<3)
#define _CACHE_CACHABLE_COW         (3<<3)  /* Au1x                    */
 
#ifdef CONFIG_MIPS_UNCACHED
#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED
#elif defined(CONFIG_DMA_NONCOHERENT)
#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT
#elif defined(CONFIG_CPU_RM9000)
#define PAGE_CACHABLE_DEFAULT _CACHE_CWB
#else
#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
#endif
 
in include/asm-mips/pgtbale.h:
#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \
   PAGE_CACHABLE_DEFAULT)
 
so, if i set a page attrubite is PAGE_READONLY, this attribute will set to pte , right? so ,
why it should shift 6 bits?

> D:
> V:
> G:
>
> and how the kernel write the this 6 bit to entrylo0/1 register?

A TLB write instruction about 5 lines further down in the code.
 
which function write those 6 bits to register? tlb_write_indexed() ? if i want set pages cache attribute is uncached/write-back , how it can set it correctly to MIPS?
 
Thanks,
Figo.zhang

 Ralf

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