why it not write those 6bits to entrylo0/1 register?

[figo zhang <figo1802@gmail.com>]

hi, all,

i have a qusetion , in arch/mips/mm/tlb-r4k.c, __update_tlb() function:

321 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)

322                 write_c0_entrylo0(ptep->pte_high);

323                 ptep++;

324                 write_c0_entrylo1(ptep->pte_high);

325 #else

326                 write_c0_entrylo0(pte_val(*ptep++) >> 6);

327                 write_c0_entrylo1(pte_val(*ptep) >> 6);

328 #endif

 

why this right shift 6 bits? this 6 bits contain some important bit, such as:

C: [bit3~5]: cohereny attribute of page

D:

V:

G:

 

and how the kernel write the this 6 bit to entrylo0/1 register?

 

Best,

Figo.zhang