| To: | myuboot@fastmail.fm |
|---|---|
| Subject: | Re: serial port 8250 messed up after coverting from little endian to big endian on kernel 2.6.31 |
| From: | Shmulik Ladkani <jungoshmulik@gmail.com> |
| Date: | Wed, 28 Oct 2009 10:35:51 +0200 |
| Cc: | "Florian Fainelli" <florian@openwrt.org>, linux-kernel@vger.kernel.org, "linux-mips" <linux-mips@linux-mips.org>, shmulik@jungo.com |
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| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <1255735395.30097.1340523469@webmail.messagingengine.com> <4AD906D8.3020404@caviumnetworks.com> <1255996564.10560.1340920621@webmail.messagingengine.com> <200910200817.24018.florian@openwrt.org> <1256676013.24305.1342273367@webmail.messagingengine.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
On Tue, 27 Oct 2009 15:40:13 -0500 myuboot@fastmail.fm wrote: > Thanks, Florian. I found the cause of the problem. My board is 32 bit > based, so each serial port register is 32bit even only 8 bit is used. So > when the board is switched endianess, I need to change the address > offset to access the same registers. > For example, original RHR register address is 0x8001000 with little > endian mode. With big endian, I need to access it as 0x8001003. I assume your uart_port's iotype is defined as UPIO_MEM32. UPIO_MEM32 makes 8250 access serial registers using readl/writel (which might be a problem for big-endian), while UPIO_MEM makes 8250 access the registers using readb/writeb. Maybe you should try UPIO_MEM (assuming hardware allows byte access). -- Shmulik Ladkani Jungo Ltd. |
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