Re: [PATCH 2/2] MIPS: Octeon: Use lockless interrupt controller operations when possible.

[Ralf Baechle <ralf@linux-mips.org>]

On Tue, Oct 13, 2009 at 08:52:29AM -0700, David Daney wrote:

> Some newer Octeon chips have registers that allow lockless operation
> of the interrupt controller.  Take advantage of them.

Good stuff.

> +/*
> + * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
> + * registers.
> + */
> +static void octeon_irq_ciu0_disable_all_v2(unsigned int irq)
> +{
> +     u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
> +     int index;
> +#ifdef CONFIG_SMP
> +     int cpu;
> +     for_each_online_cpu(cpu) {
> +             index = cpu_logical_map(cpu) * 2;
> +             cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
> +     }
> +#else
> +     index = cvmx_get_core_num() * 2;
> +     cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
> +#endif

This #ifdef should be unnecessary.  For NR_CPUS == 1 it is defined as

#define for_each_online_cpu(cpu)   for_each_cpu((cpu), cpu_online_mask)
And for NR_CPUS == 1:
#define for_each_cpu(cpu, mask)                 \
        for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask)

Iow, the loop will go away for uniprocessor kernels.

Rest looks ok at a glance.

  Ralf