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Re: [PATCH] MIPS: Don't write ones to reserved entryhi bits.

To: David Daney <ddaney@caviumnetworks.com>
Subject: Re: [PATCH] MIPS: Don't write ones to reserved entryhi bits.
From: Ralf Baechle <ralf@linux-mips.org>
Date: Fri, 2 Oct 2009 22:34:54 +0200
Cc: linux-mips@linux-mips.org
In-reply-to: <4AB129DF.8060200@caviumnetworks.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <1241812330-21041-1-git-send-email-ddaney@caviumnetworks.com> <20090527162937.GA9831@linux-mips.org> <4AB129DF.8060200@caviumnetworks.com>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.5.19 (2009-01-05)
On Wed, Sep 16, 2009 at 11:09:35AM -0700, David Daney wrote:

>>> According to the MIPS64 Privileged Resource Architecture manual, only
>>> values of zero may be written to bits 8..10 of CP0 entryhi.  We need
>>> to add masking by ASID_MASK.
>>
>> Yes, I've silently been relying on the hardware chopping off the excess
>> bits for no better reason that it saving an instruction.  One of the
>> functions you've touched is switch_mm() which is being used in context
>> switches and any changes to it will show up in context switching
>> benchmarks.
>>
>> The patch you did (and along with that some older SMTC changes by Kevin)
>> can be done slightly more elegant because we already have:
>>
>> #define cpu_asid(cpu, mm)       (cpu_context((cpu), (mm)) & ASID_MASK)
>>
>> in <asm/mmu_context.h>.
>>
>> We used to optimize the ASID managment code by code patching even, see
>> mmu_context.h in 78c388aed2b7184182c08428db1de6c872d815f5.
>>
>>   Ralf
>>
>> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
>>
>
> This is nice, but you never committed it.

Waiting for people to test it - thanks!  Committing it now.

  Ralf

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