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[PATCH 0/2] RFC: Alchemy: multiple timer base address support

To: Linux-MIPS <linux-mips@linux-mips.org>, Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH 0/2] RFC: Alchemy: multiple timer base address support
From: Manuel Lauss <manuel.lauss@googlemail.com>
Date: Sat, 22 Aug 2009 18:09:59 +0200
Cc: Manuel Lauss <manuel.lauss@gmail.com>
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The Au1300 has the SYS_ block, which incorporates the 32kHz timer, PM
support and other stuff, at a base address different from all previous
models.  The following two patches add support for runtime detection
of CPU type and setup the timer on the correct base address (and as
preparation for a later patchseries, also irq number for RTCMATCH2).

Patch overview:
#1 adds a simple CPU subtype enumerator,
#2 implements the core changes.

Run-tested on DB1200.

Manuel Lauss (2):
  Alchemy: simple cpu subtype detector.
  Alchemy: timer: support multiple SYS_BASE addresses

 arch/mips/alchemy/common/time.c            |  137 ++++++++++++++++++++--------
 arch/mips/alchemy/devboards/pm.c           |   58 +++++++-----
 arch/mips/include/asm/mach-au1x00/au1000.h |   66 ++++++++++++--
 3 files changed, 191 insertions(+), 70 deletions(-)

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