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Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus (v2).

To: David Daney <ddaney@caviumnetworks.com>
Subject: Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus (v2).
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Wed, 1 Jul 2009 02:36:31 +0100 (BST)
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
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References: <1246294455-26866-1-git-send-email-ddaney@caviumnetworks.com> <20090629193454.GA23430@linux-mips.org> <alpine.LFD.2.00.0907010132500.23134@eddie.linux-mips.org> <4A4AB845.1030906@caviumnetworks.com>
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On Tue, 30 Jun 2009, David Daney wrote:

> The problem with CPU_MIPS64_R2 in the kernel is that it means two unrelated
> things:
> 
> 1) The cpu can execute all mips64r2 ISA instructions.
> 
> 2) The cpu requires that all worse case cache and execution hazards are
> handled.
> 
> In the case of the Octeon processors, #1 is true, but we can get better
> performance by omitting many of the hazard barriers because they are unneeded.

 Which is why I think a split of the semantics would be a good idea.

  Maciej

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