On Fri, Jun 26, 2009 at 09:02:48AM -0700, David Daney wrote:
> Some CPUs implement mipsr2, but because they are a super-set of
> mips64r2 do not define CONFIG_CPU_MIPS64_R2. Cavium OCTEON falls into
> this category. We would still like to use the optimized
> implementation, so since we have already checked for
> CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of
> CONFIG_CPU_MIPS64_R2 is sufficient.
>
> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
> ---
> arch/mips/include/asm/swab.h | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/mips/include/asm/swab.h b/arch/mips/include/asm/swab.h
> index 99993c0..e5b9161 100644
> --- a/arch/mips/include/asm/swab.h
> +++ b/arch/mips/include/asm/swab.h
> @@ -38,7 +38,7 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32
> x)
> }
> #define __arch_swab32 __arch_swab32
>
> -#ifdef CONFIG_CPU_MIPS64_R2
> +#ifdef CONFIG_64BIT
You just broke support for non-R2 64-bit processors.
Ralf
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