need help for porting yamon

[tao wan <wannmt@gmail.com>]

hi，everyone！

i am porting yamon to an au1250  board which was mostly like a DBAU1200 develop board.

the different is that dbau1200 uses 4 chips` ddr2-533,but we just use 2 chips` ddr2-800, the total size is 128MB   

i am using flash programmer to burn yamon and use ocd commander to debug.

yamon was successfully burned to flash at the start address 0xbfc00000 but when it does  ram test,it failed.

 

in detail,yamon codes are executed in such a way :

reset.S---> reset_dbau1200.S---->init.S--->C code

our yamon was failed in init.S,in the branch sys_memory_setup

 

sys_memory_setup  perform a ram write and read to test whether it can work .

basicly it write to such addresses:

0xa0000000：0xaaaaaaaa
0xa0fffffc:0xfedebabe
0xa1fffffc:0xfedebabe
0xa2fffffc:0xfedebabe
0xa3fffffc:0xfedebabe
0xa4fffffc:0xfedebabe
0xa5fffffc:0xfedebabe
0xa6fffffc:0xfedebabe
0xa7fffffc:0x55555555

 

i use ocd to read ram and found it`s:

0xa0000000：0xaaaaaaaa
0xa0fffffc:0xfedebabe
0xa1fffffc:0xfedebabe
0xa2fffffc:0x00000000
0xa3fffffc:0xfedebabe
0xa4fffffc:0x00000000
0xa5fffffc:0xfedebabe
0xa6fffffc:0xfedebabe
0xa7fffffc:0x55555555

 

i try many times and it is always 0xa2fffffc and  0xa4fffffc address error.

i feel very puzzled!

i use another board and it is still the same problem.so i think it may not be a hardware problem.

it may be a wrong ram initialization.

 

what i changed in reset_db1200.S is :

 

With a DDR clock of 198MHz (sdconfigb[CR]=1), DDR clock period is 5ns

mem_sdmode: 0000 0001 0010 0111 0010 0010 0010 0100 : 0x01272224
  Twtr=001  (1+1 clocks) data sheet specs 10ns for tWTR
   Twr=010  (1+2 clocks) data sheet specs 15ns for tWR
  Tras=0111 (1+7 clocks) data sheet specs 40ns for tRAS
   Trp=010  (1+2 clocks) data sheet specs 15ns for tRP
Trcdwr=010  (1+2 clocks) data sheet specs 15ns for tRCD
Trcdrd=010  (1+2 clocks) data sheet specs 15ns for tRCD
  Tcas=100  (CL=3      ) data sheet specs CL=3 for 400mhz

mem_sdaddr: 0010 0011 0001 0000 0000 0011 1110 0000 : 0x231003E0
    BR=0    (bank,row,col)
    RS=10   (13 row)
    CS=011  (10 col)
  E=1    (enabled)
  CSBA=0000000000 (0x00000000)
CSMASK=1111100000 (0xF8000000)

mem_sdconfiga: 0011 0001 0100 0000 0000 0110 0000 1010 : 0x3140060A
     E=0    (refresh disable)
    CE=11   (both clocks enabled)
   RPT=00   (1 refresh per cycle)
   Trc=010100 (1+20 clocks) data sheet specs 55ns for tRC, 105ns for tRFC
   REF=0x60A  (1562 clocks) data sheet specs 7.8125us intervals (8K rows in 64ms)

mem_sdconfigb: 1010 0000 0000 0010 0000 0000 0000 0000 : 0xA002000C
    CR=1    (1:1)
    BW=0    (32bit wide bus)
    MT=1    (DDR2)
  PSEL=0    (addr 10 for auto precharge)
    C2=0    (core lowest priority)
    AC=00   (default)
    HP=0    (no half-pll mode)
    PM=00   (no power modes)
CKECNT=00   (n/a)
    BB=0    (normal)
    DS=1    (full drive strength)
    FS=0    (normal)
   PDX=00   (n/a)
CKEmin=00   (n/a ?)
    CB=0    (normal)
 TXARD=000  (n/a)
    BA=0    (no block)
  TXSR=001100 (1+12 * 16=208 > 200 clocks)

mem_sdwrmd:
Mode Register 0: 0000 0100 0011 0010 : 0x0432
   PD=0     Fast Exit
   WR=010   3 Clocks
  DLL=0     Normal
   TM=0     Normal
   CL=011   CL=3
   BT=0     sequential burst type
   BL=010   burst length of 4

Mode Register 1: 0000 0100 0000 0000 : 0x0400
  OUT=0     Normal drive strength
 RDQS=0     Disable
  DQS=1     Disable
  OCD=000   Not supported
  RTT=10    150 Ohm termination needed with two ranks populated
   AL=00    0
  ODS=0     100%
  DLL=0     Normal/Enable

Mode Register 2: 0x0000
Mode Register 3: 0x0000
 */
#define MEM_SDMODE0_DDR2 0x01272224
#define MEM_SDMODE1_DDR2 0x00000000
#define MEM_SDADDR0_DDR2 0x231003E0
#define MEM_SDADDR1_DDR2 0x00000000
#define MEM_SDCONFIGA_DDR2 0x3140060A
#define MEM_SDCONFIGB_DDR2 0xA002000C
#define MEM_MR0_DDR2  0x00000432
#define MEM_MR1_DDR2  0x40000440
#define MEM_MR2_DDR2  0x80000000
#define MEM_MR3_DDR2  0xC0000000

 

my ddr2 is

/*
 * SDCS0 - 64MB DDR2-800 winbond w9751g6ib (8Mbit x 16 x 4bank devices)
 *    64MB DDR2-800 winbond w9751g6ib (8Mbit x 16 x 4bank devices)
*/

could anybody give me some suggestion to this comfiguration ?

or if this is just fine what can be the probabilities to the above error?

 

another question,because au1250 doesn`t support ddr2-800,so i set our ddr2 to work as a ddr2-533,can this be OK?

 

thanks!