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[PATCH 1/2] MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.

To: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: [PATCH 1/2] MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.
From: David Daney <ddaney@caviumnetworks.com>
Date: Wed, 13 May 2009 15:59:55 -0700
Cc: David Daney <ddaney@caviumnetworks.com>
In-reply-to: <4A0B5077.2010600@caviumnetworks.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <4A0B5077.2010600@caviumnetworks.com>
Sender: linux-mips-bounce@linux-mips.org
Some CPUs have implementation dependent rdhwr registers.  Allow them
to be enabled on a per CPU basis.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 arch/mips/include/asm/cpu-features.h |    4 ++++
 arch/mips/kernel/traps.c             |    2 +-
 2 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/mips/include/asm/cpu-features.h 
b/arch/mips/include/asm/cpu-features.h
index 1cba4b2..8ab1d12 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -234,4 +234,8 @@
 #define cpu_scache_line_size() cpu_data[0].scache.linesz
 #endif
 
+#ifndef cpu_hwrena_impl_bits
+#define cpu_hwrena_impl_bits           0
+#endif
+
 #endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index c3cc42e..efcb509 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1541,7 +1541,7 @@ void __cpuinit per_cpu_trap_init(void)
                         status_set);
 
        if (cpu_has_mips_r2) {
-               unsigned int enable = 0x0000000f;
+               unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits;
 
                if (!noulri && cpu_has_userlocal)
                        enable |= (1 << 29);
-- 
1.6.0.6


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