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[PATCH 2/2] MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overri

To: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: [PATCH 2/2] MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.h
From: David Daney <ddaney@caviumnetworks.com>
Date: Wed, 13 May 2009 15:59:56 -0700
Cc: David Daney <ddaney@caviumnetworks.com>
In-reply-to: <4A0B5077.2010600@caviumnetworks.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <4A0B5077.2010600@caviumnetworks.com>
Sender: linux-mips-bounce@linux-mips.org
We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove
it to mach-cavium-octeon/cpu-feature-overrides.h

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    1 +
 arch/mips/kernel/traps.c                           |    4 ----
 2 files changed, 1 insertions(+), 4 deletions(-)

diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h 
b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bb291f4..3d83075 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -53,6 +53,7 @@
 #define cpu_has_userlocal      0
 #define cpu_has_vint           0
 #define cpu_has_veic           0
+#define cpu_hwrena_impl_bits   0xc0000000
 #define ARCH_HAS_READ_CURRENT_TIMER 1
 #define ARCH_HAS_IRQ_PER_CPU   1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index efcb509..295a584 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1549,10 +1549,6 @@ void __cpuinit per_cpu_trap_init(void)
                write_c0_hwrena(enable);
        }
 
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-       write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */
-#endif
-
 #ifdef CONFIG_MIPS_MT_SMTC
        if (!secondaryTC) {
 #endif /* CONFIG_MIPS_MT_SMTC */
-- 
1.6.0.6


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