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[PATCH 2/3] MIPS: Remove execution hazard barriers for Octeon.

To: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: [PATCH 2/3] MIPS: Remove execution hazard barriers for Octeon.
From: David Daney <ddaney@caviumnetworks.com>
Date: Tue, 12 May 2009 12:41:54 -0700
Cc: David Daney <ddaney@caviumnetworks.com>
In-reply-to: <4A09D0B1.2030305@caviumnetworks.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <4A09D0B1.2030305@caviumnetworks.com>
Sender: linux-mips-bounce@linux-mips.org
The Octeon has no execution hazards, so we can remove them and save an
instruction per TLB handler invocation.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h 
b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 04ce6e6..bb291f4 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -47,6 +47,7 @@
 #define cpu_has_mips32r2       0
 #define cpu_has_mips64r1       0
 #define cpu_has_mips64r2       1
+#define cpu_has_mips_r2_exec_hazard 0
 #define cpu_has_dsp            0
 #define cpu_has_mipsmt         0
 #define cpu_has_userlocal      0
-- 
1.6.0.6


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