[PATCH 0/3] Remove 'ehb' instructions from Cavium TLB handlers.

[David Daney <ddaney@caviumnetworks.com>]

The Cavium Octeon CPU never needs the ehb instruction, this patch set
removes it resulting in shorter TLB handler hot paths.

I will reply with the three patches.

David Daney (3):
  MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.
  MIPS: Remove execution hazard barriers for Octeon.
  MIPS: Remove dead case label.

 arch/mips/include/asm/cpu-features.h               |    4 ++++
 .../asm/mach-cavium-octeon/cpu-feature-overrides.h |    1 +
 arch/mips/mm/tlbex.c                               |    4 ++--
 3 files changed, 7 insertions(+), 2 deletions(-)