[PATCH 1/3] MIPS: added cpu_has_uncached_accelerated feature

[Zhang Le <r0bertz@gentoo.org>]

Signed-off-by: Zhang Le <r0bertz@gentoo.org>
---
 arch/mips/include/asm/cpu-features.h |    4 ++++
 arch/mips/include/asm/cpu.h          |    1 +
 arch/mips/kernel/cpu-probe.c         |    4 ++--
 3 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/mips/include/asm/cpu-features.h 
b/arch/mips/include/asm/cpu-features.h
index c0047f8..63a34d3 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -220,6 +220,10 @@
 #define cpu_has_inclusive_pcaches      (cpu_data[0].options & 
MIPS_CPU_INCLUSIVE_CACHES)
 #endif
 
+#ifndef cpu_has_uncached_accelerated
+#define cpu_has_uncached_accelerated   (cpu_data[0].options & 
MIPS_CPU_UNCACHED_ACCELERATED)
+#endif
+
 #ifndef cpu_dcache_line_size
 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz
 #endif
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 3bdc0e3..846477b 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -265,6 +265,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_VINT          0x00080000 /* CPU supports MIPSR2 vectored 
interrupts */
 #define MIPS_CPU_VEIC          0x00100000 /* CPU supports MIPSR2 external 
interrupt controller mode */
 #define MIPS_CPU_ULRI          0x00200000 /* CPU has ULRI feature */
+#define MIPS_CPU_UNCACHED_ACCELERATED  0x00400000 /* CPU has uncached 
accelerated feature */
 
 /*
  * CPU ASE encodings
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b13b8eb..1910ccf 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -547,7 +547,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, 
unsigned int cpu)
                c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
                             MIPS_CPU_FPU | MIPS_CPU_32FPR |
                             MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
-                            MIPS_CPU_LLSC;
+                            MIPS_CPU_LLSC | MIPS_CPU_UNCACHED_ACCELERATED;
                c->tlbsize = 64;
                break;
        case PRID_IMP_R12000:
@@ -576,7 +576,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, 
unsigned int cpu)
                c->isa_level = MIPS_CPU_ISA_III;
                c->options = R4K_OPTS |
                             MIPS_CPU_FPU | MIPS_CPU_LLSC |
-                            MIPS_CPU_32FPR;
+                            MIPS_CPU_32FPR | MIPS_CPU_UNCACHED_ACCELERATED;
                c->tlbsize = 64;
                break;
        }
-- 
1.6.2.3