| To: | Thomas Bogendoerfer <tsbogend@alpha.franken.de> |
|---|---|
| Subject: | Re: [PATCH][MIPS] Use CP0 Count register to implement more granular ndelay |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Fri, 13 Mar 2009 12:32:38 +0100 |
| Cc: | VomLehn <dvomlehn@cisco.com>, Linux MIPS Mailing List <linux-mips@linux-mips.org> |
| In-reply-to: | <20090313092906.GA6526@alpha.franken.de> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <20090312032850.GA9379@cuplxvomd02.corp.sa.net> <20090313092906.GA6526@alpha.franken.de> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.5.18 (2008-05-17) |
On Fri, Mar 13, 2009 at 10:29:07AM +0100, Thomas Bogendoerfer wrote: > > +config MIPS4 > > + bool > > + default y if CPU_R8000 || CPU_R10000 > > + > > what about all the R5k CPUs ? There is cpu_has_counter which return if a processor actually has a cp0 counter. Also cpu_has_mfc0_count_bug() which indicates usability of the counter. The cp0 counter should rather not be used on early R4000 processors, for example. Ralf |
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