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Re: [PATCH][MIPS] Use CP0 Count register to implement more granular ndel

To: VomLehn <dvomlehn@cisco.com>
Subject: Re: [PATCH][MIPS] Use CP0 Count register to implement more granular ndelay
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 10 Mar 2009 21:12:25 +0100
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>, linux-mips@linux-mips.org
In-reply-to: <20090310191828.GA30449@cuplxvomd02.corp.sa.net>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20090227230950.GA29546@cuplxvomd02.corp.sa.net> <7d1d9c250902281310o7c03da24jcb8760fdfef4d46b@mail.gmail.com> <20090310191828.GA30449@cuplxvomd02.corp.sa.net>
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On Tue, Mar 10, 2009 at 12:18:28PM -0700, VomLehn wrote:

> > > +config CP0_COUNT_NDELAY
> > > +       bool "Use coprocessor 0 Count register for ndelay functionality"
> > > +       default n
> > 
> > Does there need to be some sort of depends here to cover off any
> > limitations where it is known that it won't work?
> 
> I don't have the breadth of knowledge required to say what processors have
> a CP0 Count register. Any suggestions?

All MIPS III, MIPS IV, MIPS32 and MIPS64 processors have a 32-bit count
register which typically is clocked at half the maximum instruction issue
rate, more rarely at the full rate.  A few processors like the RM53230
family can select the increment rate at reset-time to either the full or
half instruction issue rate.  Others have the option of totally halting
it in special low-power, low-performance modes.  The count rate might also
be affected by clock scaling.

  Ralf

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