linux-mips
[Top] [All Lists]

[PATCH] MIPS: Only allow Cavium OCTEON to be configured for boards that

To: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: [PATCH] MIPS: Only allow Cavium OCTEON to be configured for boards that support it (v2).
From: David Daney <ddaney@caviumnetworks.com>
Date: Mon, 2 Feb 2009 11:30:59 -0800
Cc: David Daney <ddaney@caviumnetworks.com>, Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
CC: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---

I thought I sent this before, but I can't find evidence of that, So
here it is again.

 arch/mips/Kconfig |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 600eef3..cb76d16 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -603,7 +603,7 @@ config CAVIUM_OCTEON_SIMULATOR
        select SYS_SUPPORTS_64BIT_KERNEL
        select SYS_SUPPORTS_BIG_ENDIAN
        select SYS_SUPPORTS_HIGHMEM
-       select CPU_CAVIUM_OCTEON
+       select SYS_HAS_CPU_CAVIUM_OCTEON
        help
          The Octeon simulator is software performance model of the Cavium
          Octeon Processor. It supports simulating Octeon processors on x86
@@ -618,7 +618,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
        select SYS_SUPPORTS_BIG_ENDIAN
        select SYS_SUPPORTS_HIGHMEM
        select SYS_HAS_EARLY_PRINTK
-       select CPU_CAVIUM_OCTEON
+       select SYS_HAS_CPU_CAVIUM_OCTEON
        select SWAP_IO_SPACE
        help
          This option supports all of the Octeon reference boards from Cavium
@@ -1234,6 +1234,7 @@ config CPU_SB1
 
 config CPU_CAVIUM_OCTEON
        bool "Cavium Octeon processor"
+       depends on SYS_HAS_CPU_CAVIUM_OCTEON
        select IRQ_CPU
        select IRQ_CPU_OCTEON
        select CPU_HAS_PREFETCH
@@ -1314,6 +1315,9 @@ config SYS_HAS_CPU_RM9000
 config SYS_HAS_CPU_SB1
        bool
 
+config SYS_HAS_CPU_CAVIUM_OCTEON
+       bool
+
 #
 # CPU may reorder R->R, R->W, W->R, W->W
 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
-- 
1.5.6.6


<Prev in Thread] Current Thread [Next in Thread>