Re: [PATCH 20/20] MIPS: Add Cavium OCTEON to arch/mips/Kconfig

[Atsushi Nemoto <anemo@mba.ocn.ne.jp>]

On Thu, 11 Dec 2008 15:33:38 -0800, David Daney <ddaney@caviumnetworks.com> 
wrote:
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -595,6 +595,44 @@ config WR_PPMC
>         This enables support for the Wind River MIPS32 4KC PPMC evaluation
>         board, which is based on GT64120 bridge chip.
>  
> +config CAVIUM_OCTEON_SIMULATOR
> +     bool "Support for the Cavium Networks Octeon Simulator"
> +     select CEVT_R4K
> +     select 64BIT_PHYS_ADDR
> +     select DMA_COHERENT
> +     select SYS_SUPPORTS_64BIT_KERNEL
> +     select SYS_SUPPORTS_BIG_ENDIAN
> +     select SYS_SUPPORTS_HIGHMEM
> +     select CPU_CAVIUM_OCTEON
> +     help
> +       The Octeon simulator is software performance model of the Cavium
> +       Octeon Processor. It supports simulating Octeon processors on x86
> +       hardware.

All other board entries use SYS_HAS_CPU_XXXX intermediate variable to
select CPU.  Please defined SYS_HAS_CPU_CAVIUM_OCTEON and use it.
Othersize every other board configs will be asked for
CPU_CAVIUM_OCTEON.

---
Atsushi Nemoto