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[PATCH 0/2] PCI support for Cavium OCTEON processors.

To: linux-mips <linux-mips@linux-mips.org>
Subject: [PATCH 0/2] PCI support for Cavium OCTEON processors.
From: David Daney <ddaney@caviumnetworks.com>
Date: Fri, 19 Dec 2008 15:18:25 -0800
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
User-agent: Thunderbird 2.0.0.18 (X11/20081119)
This patch adds preliminary support for PCI and PCIe to the initial
processor support patch that is queued for 2.6.29 (actually it is
against a slightly changed version of that patch set).  It has been
tested with both an RT8139 (PCI ethernet) and e1000e (PCIe ethernet)
on several different boards and seems to be working well.

There are two patches, the first adds register definitions needed by
PCI and PCIe, the second is the main patch that adds the support.


Any comments are welcome.


I will reply with two patches.

David Daney (2):
 MIPS: Add register definitions for PCI.
 MIPS: Add Cavium OCTEON PCI support.

arch/mips/Kconfig                                  |    2 +
arch/mips/cavium-octeon/Makefile                   |    4 +
arch/mips/cavium-octeon/dma-octeon.c               |  310 +++-
arch/mips/cavium-octeon/executive/Makefile         |    2 +
.../cavium-octeon/executive/cvmx-helper-errata.c   |  379 +++
.../cavium-octeon/executive/cvmx-helper-util.c     |  502 ++++
arch/mips/cavium-octeon/executive/cvmx-pcie.c      | 1053 ++++++++
arch/mips/cavium-octeon/msi.c                      |  288 +++
arch/mips/cavium-octeon/octeon-irq.c               |    2 +
arch/mips/cavium-octeon/pci-common.c               |  137 ++
arch/mips/cavium-octeon/pci-common.h               |   39 +
arch/mips/cavium-octeon/pci.c                      |  568 +++++
arch/mips/cavium-octeon/pcie.c                     |  441 ++++
arch/mips/include/asm/octeon/cvmx-asm.h            |    3 +-
arch/mips/include/asm/octeon/cvmx-helper-errata.h  |   92 +
arch/mips/include/asm/octeon/cvmx-helper-util.h    |  266 ++
arch/mips/include/asm/octeon/cvmx-npei-defs.h      | 2560 ++++++++++++++++++++
arch/mips/include/asm/octeon/cvmx-npi-defs.h       | 1735 +++++++++++++
arch/mips/include/asm/octeon/cvmx-packet.h         |   16 +-
arch/mips/include/asm/octeon/cvmx-pci-defs.h       | 1645 +++++++++++++
arch/mips/include/asm/octeon/cvmx-pcie.h           |  284 +++
arch/mips/include/asm/octeon/cvmx-pcieep-defs.h    | 1365 +++++++++++
arch/mips/include/asm/octeon/cvmx-pciercx-defs.h   | 1397 +++++++++++
arch/mips/include/asm/octeon/cvmx-pescx-defs.h     |  410 ++++
arch/mips/include/asm/octeon/cvmx-pexp-defs.h      |  229 ++
arch/mips/include/asm/octeon/cvmx-wqe.h            |  422 ++++
arch/mips/include/asm/octeon/cvmx.h                |   12 +
arch/mips/include/asm/octeon/octeon.h              |    2 +
28 files changed, 14157 insertions(+), 8 deletions(-)
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-util.c
create mode 100644 arch/mips/cavium-octeon/executive/cvmx-pcie.c
create mode 100644 arch/mips/cavium-octeon/msi.c
create mode 100644 arch/mips/cavium-octeon/pci-common.c
create mode 100644 arch/mips/cavium-octeon/pci-common.h
create mode 100644 arch/mips/cavium-octeon/pci.c
create mode 100644 arch/mips/cavium-octeon/pcie.c
create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-errata.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-util.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-npei-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-npi-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-pci-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-pcie.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-pescx-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-pexp-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-wqe.h


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