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Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus.

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus.
From: David Daney <ddaney@caviumnetworks.com>
Date: Thu, 18 Dec 2008 08:42:07 -0800
Cc: linux-mips@linux-mips.org
In-reply-to: <20081218080740.GA15338@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <1229546644-3030-1-git-send-email-ddaney@caviumnetworks.com> <20081218080740.GA15338@linux-mips.org>
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Ralf Baechle wrote:
On Wed, Dec 17, 2008 at 12:44:04PM -0800, David Daney wrote:

Some CPUs implement mipsr2, but because they are a super-set of
mips64r2 do not define CONFIG_CPU_MIPS64_R2.  Cavium OCTEON falls into
this category.  We would still like to use the optimized
implementation, so since we have already checked for
CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of
CONFIG_CPU_MIPS64_R2 is sufficient.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 arch/mips/include/asm/byteorder.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/mips/include/asm/byteorder.h 
b/arch/mips/include/asm/byteorder.h
index 2988d29..92ec1e1 100644
--- a/arch/mips/include/asm/byteorder.h
+++ b/arch/mips/include/asm/byteorder.h
@@ -46,7 +46,7 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
 }
 #define __arch_swab32 __arch_swab32
-#ifdef CONFIG_CPU_MIPS64_R2
+#ifdef CONFIG_64BIT

This breaks every non-R2 64-bit processor.

I disagree. As I said before, the entire block is wrapped by #ifdef MIPS_R2. non-R2 processors will not get any of the optimized byte swapping code. I just want to allow all 64 bit R2 processors to use the optimized code.

David Daney

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