[PATCH 18/26] MIPS: Add Cavium OCTEON slot into proper tlb category.

[David Daney <ddaney@caviumnetworks.com>]

Expand the case statement for build_tlb_write_entry so that it does
the right thing on Cavium CPU variants.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 arch/mips/mm/tlbex.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 979cf91..4294203 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -317,6 +317,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct 
uasm_label **l,
        case CPU_BCM3302:
        case CPU_BCM4710:
        case CPU_LOONGSON2:
+       case CPU_CAVIUM_OCTEON:
                if (m4kc_tlbp_war())
                        uasm_i_nop(p);
                tlbw(p);
-- 
1.5.6.5