[PATCH 18/29] MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family.

To:	linux-mips@linux-mips.org
Subject:	[PATCH 18/29] MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family.
From:	David Daney <ddaney@caviumnetworks.com>
Date:	Thu, 6 Nov 2008 12:54:31 -0800
Cc:	David Daney <ddaney@caviumnetworks.com>, Tomaso Paoletti <tpaoletti@caviumnetworks.com>, Paul Gortmaker <Paul.Gortmaker@windriver.com>
In-reply-to:	<491358F5.7040002@caviumnetworks.com>
Original-recipient:	rfc822;linux-mips@linux-mips.org
References:	<491358F5.7040002@caviumnetworks.com>
Sender:	linux-mips-bounce@linux-mips.org

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 arch/mips/include/asm/smp.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 0ff5b52..e6f419f 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -37,6 +37,9 @@ extern int __cpu_logical_map[NR_CPUS];
 
 #define SMP_RESCHEDULE_YOURSELF        0x1     /* XXX braindead */
 #define SMP_CALL_FUNCTION      0x2
+/* Octeon - Tell another core to flush its icache */
+#define SMP_ICACHE_FLUSH       0x4
+
 
 extern cpumask_t phys_cpu_present_map;
 #define cpu_possible_map       phys_cpu_present_map
-- 
1.5.6.5

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[PATCH 07/29] MIPS: For Cavium OCTEON set hwrena and lazily restore CP2 state., (continued) [PATCH 07/29] MIPS: For Cavium OCTEON set hwrena and lazily restore CP2 state., David Daney [PATCH 09/29] MIPS: Add Cavium OCTEON processor constants., David Daney [PATCH 10/29] MIPS: Add Cavium OCTEON specific register definitions to mipsregs.h, David Daney [PATCH 11/29] MIPS: Override assembler target architecture for octeon., David Daney [PATCH 12/29] MIPS: Probe for Cavium OCTEON CPUs., David Daney [PATCH 13/29] MIPS: Hook Cavium OCTEON cache init into cache.c, David Daney [PATCH 14/29] MIPS: Hook up Cavium OCTEON in arch/mips., David Daney [PATCH 15/29] MIPS: Modify core io.h macros to account for the Octeon Errata Core-301., David Daney [PATCH 16/29] MIPS: Add Cavium OCTEON cop2/cvmseg state entries to processor.h., David Daney [PATCH 17/29] MIPS: Add Cavium OCTEON specific registers to ptrace.h and asm-offsets.c, David Daney [PATCH 18/29] MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family., David Daney <= Re: [PATCH 18/29] MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family., Sergei Shtylyov Re: [PATCH 18/29] MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family., David Daney Re: [PATCH 18/29] MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family., Sergei Shtylyov Re: [PATCH 18/29] MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family., David Daney Re: [PATCH 18/29] MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family., Sergei Shtylyov Re: [PATCH 18/29] MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family., Maciej W. Rozycki [PATCH 19/29] MIPS: Cavium OCTEON: PT vs MFC0 reorder, multiplier state preservation., David Daney [PATCH 20/29] MIPS: Add Cavium OCTEON irq hazard in asmmacro.h., David Daney [PATCH 21/29] MIPS: Compute branch returns for Cavium OCTEON specific branch instructions., David Daney [PATCH 22/29] MIPS: Add Cavium OCTEON slot into proper tlb category., David Daney

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