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RE: [PATCH]: R10000 Needs LL/SC Workaround in Gcc

Subject: RE: [PATCH]: R10000 Needs LL/SC Workaround in Gcc
From: "Maciej W. Rozycki" <>
Date: Mon, 3 Nov 2008 16:59:05 +0000 (GMT)
In-reply-to: <>
Original-recipient: rfc822;
References: <> <> <87abcjibsl.fsf@firetop.home> <> <87tzargrn4.fsf@firetop.home> <> <> <>
User-agent: Alpine 1.10 (LFD 962 2008-03-14)
On Mon, 3 Nov 2008, wrote:

> > I believe (but have not checked) that all CPUs/ISAs that are within the 
> >MIPS II - MIPS IV range enable -mbranch-likely by default, 
> Not quite.  sb1 has no-branch-likely.  It actually does implement the 
> instruction but the documentation clearly states that it should be 
> avoided.

 Well, the SB-1 is a MIPS architecture processor (a MIPS64 one to be 
exact) and as such not within the MIPS II - MIPS IV ISA range and what you 
say by definition stands for any other MIPS architecture implementation 
too.  This is not relevant though as MIPS64 code won't run on a MIPS IV 
processor such as the R10k anyway.


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