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[patch 1/3] mips: use the new byteorder headers

To: ralf@linux-mips.org
Subject: [patch 1/3] mips: use the new byteorder headers
From: akpm@linux-foundation.org
Date: Wed, 29 Oct 2008 14:21:32 -0700
Cc: linux-mips@linux-mips.org, akpm@linux-foundation.org, harvey.harrison@gmail.com
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
From: Harvey Harrison <harvey.harrison@gmail.com>

Acked-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---

 arch/mips/include/asm/byteorder.h |   40 +++++++++++-----------------
 1 file changed, 16 insertions(+), 24 deletions(-)

diff -puN arch/mips/include/asm/byteorder.h~mips-use-the-new-byteorder-headers 
arch/mips/include/asm/byteorder.h
--- a/arch/mips/include/asm/byteorder.h~mips-use-the-new-byteorder-headers
+++ a/arch/mips/include/asm/byteorder.h
@@ -11,11 +11,19 @@
 #include <linux/compiler.h>
 #include <asm/types.h>
 
-#ifdef __GNUC__
+#if defined(__MIPSEB__)
+# define __BIG_ENDIAN
+#elif defined(__MIPSEL__)
+# define __LITTLE_ENDIAN
+#else
+# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
+#endif
+
+#define __SWAB_64_THRU_32__
 
 #ifdef CONFIG_CPU_MIPSR2
 
-static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
 {
        __asm__(
        "       wsbh    %0, %1                  \n"
@@ -24,9 +32,9 @@ static __inline__ __attribute_const__ __
 
        return x;
 }
-#define __arch__swab16(x)      ___arch__swab16(x)
+#define __arch_swab16 __arch_swab16
 
-static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
 {
        __asm__(
        "       wsbh    %0, %1                  \n"
@@ -36,11 +44,10 @@ static __inline__ __attribute_const__ __
 
        return x;
 }
-#define __arch__swab32(x)      ___arch__swab32(x)
+#define __arch_swab32 __arch_swab32
 
 #ifdef CONFIG_CPU_MIPS64_R2
-
-static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
+static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
 {
        __asm__(
        "       dsbh    %0, %1                  \n"
@@ -51,26 +58,11 @@ static __inline__ __attribute_const__ __
 
        return x;
 }
-
-#define __arch__swab64(x)      ___arch__swab64(x)
-
+#define __arch_swab64 __arch_swab64
 #endif /* CONFIG_CPU_MIPS64_R2 */
 
 #endif /* CONFIG_CPU_MIPSR2 */
 
-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-
-#endif /* __GNUC__ */
-
-#if defined(__MIPSEB__)
-#  include <linux/byteorder/big_endian.h>
-#elif defined(__MIPSEL__)
-#  include <linux/byteorder/little_endian.h>
-#else
-#  error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
-#endif
+#include <linux/byteorder.h>
 
 #endif /* _ASM_BYTEORDER_H */
_

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