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Re: [PATCH 15/36] Probe for Cavium OCTEON CPUs.

To: David Daney <ddaney@caviumnetworks.com>
Subject: Re: [PATCH 15/36] Probe for Cavium OCTEON CPUs.
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Wed, 29 Oct 2008 19:24:44 +0000 (GMT)
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org, Tomaso Paoletti <tpaoletti@caviumnetworks.com>, Paul Gortmaker <Paul.Gortmaker@windriver.com>
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On Wed, 29 Oct 2008, David Daney wrote:

> R4400 and R10K have the watch registers, but they do not have mips semantics,
> so are not currently usable with the watch register support.   This is why I
> initially was very conservative about the conditions under which I probed
> watch registers.  So I think it is good to try to verify these things.

 Neither is a MIPS architecture processor -- they are legacy MIPS III and 
MIPS IV processors, respectively, and as such do not have a MIPS-compliant 
set of CP0 Config registers nor they support the select specifier for 
coprocessor transfer operations (although unlike some earlier 
implementations they do have a CP0.Config register).  Watchpoint support 
would have to be done specifically for them; as I have a moderate interest 
in it and I have R4000/R4400 hardware, I may look into it eventually (but 
then, I have meant so for some last six years or so, so...).  The same 
applies to the R4650 which defines watchpoints in yet a different way, but 
that one does not have an MMU, so we can safely skip it for the time 
being.

  Maciej

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