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Re: [PATCH 15/36] Probe for Cavium OCTEON CPUs.

To: David Daney <ddaney@caviumnetworks.com>
Subject: Re: [PATCH 15/36] Probe for Cavium OCTEON CPUs.
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 29 Oct 2008 17:10:15 +0000
Cc: linux-mips@linux-mips.org, Tomaso Paoletti <tpaoletti@caviumnetworks.com>, Paul Gortmaker <Paul.Gortmaker@windriver.com>
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On Wed, Oct 29, 2008 at 09:31:51AM -0700, David Daney wrote:

>> The watch bit is a standard feature of the MIPS R1/R2 architecture.  What
>> Sandcraft did was bascially an RM7000 clone with some extensions.  I'm
>> still trying to track somebody who could verify the correctness of that
>> code as I don't have Sandcraft docs ...
>>
>
> R4400 and R10K have the watch registers, but they do not have mips  
> semantics, so are not currently usable with the watch register support.   
> This is why I initially was very conservative about the conditions under 
> which I probed watch registers.  So I think it is good to try to verify 
> these things.

All the esotheric stuff really is covered in cpu_probe_legacy.  Anything
else should comply with MIPS32/MIPS64.  Exceptions apply.

Thanks to an old advertisment leaflet I was able to find that the Sandcraft
SR71000 is indeed a MIPS64 processor, so the patch was right.

  Ralf

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