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Re: [PATCH 15/36] Probe for Cavium OCTEON CPUs.

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH 15/36] Probe for Cavium OCTEON CPUs.
From: David Daney <ddaney@caviumnetworks.com>
Date: Wed, 29 Oct 2008 09:31:51 -0700
Cc: linux-mips@linux-mips.org, Tomaso Paoletti <tpaoletti@caviumnetworks.com>, Paul Gortmaker <Paul.Gortmaker@windriver.com>
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Ralf Baechle wrote:
On Wed, Oct 29, 2008 at 09:18:07AM -0700, David Daney wrote:

Acked-by: David Daney <ddaney@caviumnetworks.com>

This seems sane to me assuming that alchemy, sibyte, sandcraft, nxp, and broadcom all have standard mips{32,64} watch registers (i.e., if the watch bit in config1 is set the registers have mips semantics).

The watch bit is a standard feature of the MIPS R1/R2 architecture.  What
Sandcraft did was bascially an RM7000 clone with some extensions.  I'm
still trying to track somebody who could verify the correctness of that
code as I don't have Sandcraft docs ...


R4400 and R10K have the watch registers, but they do not have mips semantics, so are not currently usable with the watch register support. This is why I initially was very conservative about the conditions under which I probed watch registers. So I think it is good to try to verify these things.

David Daney

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