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Re: [PATCH 15/36] Probe for Cavium OCTEON CPUs.

To: David Daney <ddaney@caviumnetworks.com>
Subject: Re: [PATCH 15/36] Probe for Cavium OCTEON CPUs.
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 29 Oct 2008 16:26:42 +0000
Cc: linux-mips@linux-mips.org, Tomaso Paoletti <tpaoletti@caviumnetworks.com>, Paul Gortmaker <Paul.Gortmaker@windriver.com>
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On Wed, Oct 29, 2008 at 09:18:07AM -0700, David Daney wrote:

> Acked-by: David Daney <ddaney@caviumnetworks.com>
>
> This seems sane to me assuming that alchemy, sibyte, sandcraft, nxp, and  
> broadcom all have standard mips{32,64} watch registers (i.e., if the  
> watch bit in config1 is set the registers have mips semantics).

The watch bit is a standard feature of the MIPS R1/R2 architecture.  What
Sandcraft did was bascially an RM7000 clone with some extensions.  I'm
still trying to track somebody who could verify the correctness of that
code as I don't have Sandcraft docs ...

  Ralf

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