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Re: [PATCH 15/36] Probe for Cavium OCTEON CPUs.

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH 15/36] Probe for Cavium OCTEON CPUs.
From: David Daney <ddaney@caviumnetworks.com>
Date: Wed, 29 Oct 2008 09:18:07 -0700
Cc: linux-mips@linux-mips.org, Tomaso Paoletti <tpaoletti@caviumnetworks.com>, Paul Gortmaker <Paul.Gortmaker@windriver.com>
In-reply-to: <20081029121737.GA26256@linux-mips.org>
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Ralf Baechle wrote:
[...]

We probably should move the mips_probe_watch_registers() into
mips_probe_watch_registers().  I notice the function is only getting
called from cpu_probe_mips().  Iow the watch register support won't work
for CPUs made by any other vendor.  So I suggest below patch.  Plus
all of the above patch sans the mips_probe_watch_registers call on top.

  Ralf

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 0cf1545..008230f 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c

Acked-by: David Daney <ddaney@caviumnetworks.com>

This seems sane to me assuming that alchemy, sibyte, sandcraft, nxp, and broadcom all have standard mips{32,64} watch registers (i.e., if the watch bit in config1 is set the registers have mips semantics).

David Daney

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