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Re: [PATCH 11/36] MIPSR2 ebase isn't just CAC_BASE

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH 11/36] MIPSR2 ebase isn't just CAC_BASE
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Tue, 28 Oct 2008 17:29:23 +0000 (GMT)
Cc: Chad Reese <kreese@caviumnetworks.com>, David Daney <ddaney@caviumnetworks.com>, linux-mips@linux-mips.org, Tomaso Paoletti <tpaoletti@caviumnetworks.com>
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On Tue, 28 Oct 2008, Ralf Baechle wrote:

> I see your point.  If we dynamically allocate memory for exception handlers
> at run-time and point ebase to it multi-kernel systems should till work
> unless maybe the firmware gets disturbed by such a change of ebase.

 A run-time sanity check would do I suppose.  I.e. that ebase points to 
somewhere within installed RAM and does not clash with the kernel in some 
way.  We can mark that page as reserved in the memory map then; something 
we ought to regardless and which I gather we do not at the moment.

  Maciej

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