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Re: [PATCH 11/36] MIPSR2 ebase isn't just CAC_BASE

To: Chad Reese <kreese@caviumnetworks.com>
Subject: Re: [PATCH 11/36] MIPSR2 ebase isn't just CAC_BASE
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 28 Oct 2008 16:27:41 +0000
Cc: "Maciej W. Rozycki" <macro@linux-mips.org>, David Daney <ddaney@caviumnetworks.com>, linux-mips@linux-mips.org, Tomaso Paoletti <tpaoletti@caviumnetworks.com>
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On Tue, Oct 28, 2008 at 09:13:44AM -0700, Chad Reese wrote:

> From an Octeon perspective, we'd prefer that the kernel not touch ebase
> as we set it in the bootloader. The bootloader sets the proper value
> based on the number of kernels being loaded and which cores the kernel
> is loaded on. This allows some interesting things, like running 16
> kernels each on a different CPU. Although 16 kernels is just a toy
> project, we have a number of customers that run two kernels. They choose
> which cores the kernels run on dynamically at boot time.

I see your point.  If we dynamically allocate memory for exception handlers
at run-time and point ebase to it multi-kernel systems should till work
unless maybe the firmware gets disturbed by such a change of ebase.

  Ralf

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