From: David Daney <ddaney@caviumnetworks.com>
Always set ST0_KX on Octeon since IO addresses are at 64bit addresses.
Keep in mind this also moves the TLB handler.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/kernel/head.S | 12 ++++++++++--
arch/mips/kernel/traps.c | 7 +++++++
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index 492a0a8..dcd0be5 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -106,7 +106,11 @@
.endm
.macro setup_c0_status_pri
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_CAVIUM_OCTEON)
+ /*
+ * Note: We always set ST0_KX on Octeon since IO addresses are at
+ * 64bit addresses. Keep in mind this also moves the TLB handler.
+ */
setup_c0_status ST0_KX 0
#else
setup_c0_status 0 0
@@ -114,7 +118,11 @@
.endm
.macro setup_c0_status_sec
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_CAVIUM_OCTEON)
+ /*
+ * Note: We always set ST0_KX on Octeon since IO addresses are at
+ * 64bit addresses. Keep in mind this also moves the TLB handler.
+ */
setup_c0_status ST0_KX ST0_BEV
#else
setup_c0_status 0 ST0_BEV
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 91c7aa2..8bed9a8 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1472,6 +1472,13 @@ void __cpuinit per_cpu_trap_init(void)
#ifdef CONFIG_64BIT
status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
#endif
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ /*
+ * Note: We always set ST0_KX on Octeon since IO addresses are at
+ * 64bit addresses. Keep in mind this also moves the TLB handler.
+ */
+ status_set |= ST0_KX;
+#endif
if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
status_set |= ST0_XX;
if (cpu_has_dsp)
--
1.5.5.1
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