[PATCH 20/37] Cavium OCTEON: add in icache and dcache error functions.

[ddaney@caviumnetworks.com]

From: David Daney <ddaney@caviumnetworks.com>

If there is an icache or dcache error, there is additional data to
be had from the 64bit read of c0 @ $27.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 arch/mips/include/asm/mipsregs.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 9798660..4a1feb5 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -966,7 +966,12 @@ do {                                                       
                \
 #define read_c0_derraddr0()    __read_ulong_c0_register($26, 1)
 #define write_c0_derraddr0(val)        __write_ulong_c0_register($26, 1, val)
 
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define read_c0_cacheerr()     __read_64bit_c0_register($27, 0)
+#define write_c0_cacheerr(val) __write_64bit_c0_register($27, 0, val)
+#else
 #define read_c0_cacheerr()     __read_32bit_c0_register($27, 0)
+#endif
 
 #define read_c0_derraddr1()    __read_ulong_c0_register($27, 1)
 #define write_c0_derraddr1(val)        __write_ulong_c0_register($27, 1, val)
-- 
1.5.5.1