[PATCH 11/37] Cavium OCTEON: ebase isn't just CAC_BASE

[ddaney@caviumnetworks.com]

From: David Daney <ddaney@caviumnetworks.com>

On Cavium, the ebase isn't just CAC_BASE, but also the part of
read_c0_ebase() too.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 arch/mips/kernel/traps.c |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 8e40795..91c7aa2 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1610,7 +1610,11 @@ void __init trap_init(void)
        if (cpu_has_veic || cpu_has_vint)
                ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + 
VECTORSPACING*64);
        else
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+               ebase = CAC_BASE + (read_c0_ebase() & 0x3ffff000);
+#else
                ebase = CAC_BASE;
+#endif
 
        per_cpu_trap_init();
 
@@ -1718,11 +1722,11 @@ void __init trap_init(void)
 
        if (cpu_has_vce)
                /* Special exception: R4[04]00 uses also the divec space. */
-               memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
+               memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
        else if (cpu_has_4kex)
-               memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
+               memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
        else
-               memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
+               memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
 
        signal_init();
 #ifdef CONFIG_MIPS32_COMPAT
-- 
1.5.5.1