| To: | htejun@gmail.com |
|---|---|
| Subject: | Re: [PATCH 1/2] ide: Add tx4939ide driver |
| From: | Atsushi Nemoto <anemo@mba.ocn.ne.jp> |
| Date: | Tue, 30 Sep 2008 22:07:22 +0900 (JST) |
| Cc: | bzolnier@gmail.com, sshtylyov@ru.mvista.com, linux-mips@linux-mips.org, linux-ide@vger.kernel.org, ralf@linux-mips.org, jens.axboe@oracle.com, James.Bottomley@HansenPartnership.com |
| In-reply-to: | <48DEAF1F.8040200@gmail.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <20080913.005904.07457691.anemo@mba.ocn.ne.jp> <200809271819.19510.bzolnier@gmail.com> <48DEAF1F.8040200@gmail.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
On Sun, 28 Sep 2008 07:09:35 +0900, Tejun Heo <htejun@gmail.com> wrote: > >>>> Do you mean __ide_flush_dcache_range? This is needed to avoid cache > >>>> inconsistency on PIO drive. PIO transfer only writes to cache but > >>>> upper layers expects the data is in main memory. > >>> Hum, then I wonder why it's MIPS specific... > >> SPARC also have it. And there were some discussions for ARM IIRC. > > > > I was under the impression that it has been addressed by Tejun at > > the higher-layer level (for both ide/libata) long time ago and that > > MIPS/SPARC code are just a left-overs which could be removed now? > > cc'ing Jens and James. IIRC, I posted several patches but they never > went in. I don't remember what the objections were or whether any > alternative fix went in. I suppose you mean thread http://lkml.org/lkml/2006/1/13/156. IIUC flushing in ide string ops is still needed for MIPS. --- Atsushi Nemoto |
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