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Re: [PATCH 1/2] ide: Add tx4939ide driver

To: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
From: Ralf Baechle <ralf@linux-mips.org>
Date: Sun, 28 Sep 2008 09:41:06 +0100
Cc: Atsushi Nemoto <anemo@mba.ocn.ne.jp>, sshtylyov@ru.mvista.com, linux-mips@linux-mips.org, linux-ide@vger.kernel.org, Tejun Heo <htejun@gmail.com>
In-reply-to: <200809271819.19510.bzolnier@gmail.com>
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On Sat, Sep 27, 2008 at 06:19:19PM +0200, Bartlomiej Zolnierkiewicz wrote:

> > > >>>+      __ide_flush_dcache_range((unsigned long)addr, size);
> > > 
> > > >>   Why is this needed BTW?
> > > 
> > > > Do you mean __ide_flush_dcache_range?  This is needed to avoid cache
> > > > inconsistency on PIO drive.  PIO transfer only writes to cache but
> > > > upper layers expects the data is in main memory.
> > > 
> > >     Hum, then I wonder why it's MIPS specific...
> > 
> > SPARC also have it.  And there were some discussions for ARM IIRC.

It should affect any architecture that has virtually indexed data caches
with aliases.

> I was under the impression that it has been addressed by Tejun at
> the higher-layer level (for both ide/libata) long time ago and that
> MIPS/SPARC code are just a left-overs which could be removed now?

I'd highly appreciate that.  The __ide_ins? / __ide_outs? ops don't know
if a page is mapped to userspace so will have to do unnecessary flushes.
A mechanism that allows flush_dcache_page to be used would be far
preferable.

  Ralf

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