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Re: MIPS checksum bug

To: ralf@linux-mips.org
Subject: Re: MIPS checksum bug
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Sat, 20 Sep 2008 22:45:30 +0900 (JST)
Cc: macro@linux-mips.org, u1@terran.org, linux-mips@linux-mips.org
In-reply-to: <20080920001344.GC31314@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20080920.004319.93205397.anemo@mba.ocn.ne.jp> <Pine.LNX.4.55.0809191656030.29711@cliff.in.clinika.pl> <20080920001344.GC31314@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
On Sat, 20 Sep 2008 02:13:44 +0200, Ralf Baechle <ralf@linux-mips.org> wrote:
> > > +#ifdef USE_DOUBLE
> > > + add     t1, zero        /* clear upper 32bit */
> > > +#endif
> > >   PTR_ADDIU       src, 4
> > >   ADDC(sum, t1)
> > >  
> > 
> >  Unfortunately you can't zero-extend with a single instruction (you can
> > use a single sll(v) to sign-extend), unless the R2 ISA provides some
> > suitable oddity (which I haven't checked).  You want something like:
> > 
> >     dsll32  t1, t1, 0
> >     dsrl32  t1, t1, 0
> > 
> > instead.
> 
> For a one's complement checksum it doesn't matter in which of the 4
> halfwords the data ends is loaded.  So the easiest solution is:
> 
>       /* Still a full word to go  */
>       ulw     t1, (src)
> #ifdef USE_DOUBLE
>       dsll    t1, t1, 32              /* clear lower 32bit */
> #endif
>       PTR_ADDIU       src, 4
>       ADDC(sum, t1)

Oops, my fault.  Thank you all.

---
Atsushi Nemoto

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